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| Preliminary PM5374 TSE-160 160 Gbit/s Transport Switching Element FEATURES * Supports multiple fabric architectures that range from 160 Gbit/s (one PM5374 TSE-160) to 640 Gbit/s (four TSE-160 devices) in a single stage, and beyond 10 Tbit/s using multi-stage fabrics. * Implements a Time-Space-Time fabric with STS-1/AU-3 granularity. * Provides Test Port functionality with 65th port. Transmit test port can snoop on any data arriving at a single receive link, or any data departing a single transmit link. Receive Test Port can be used to inject arbitrary data into the device. * Provides two independent time domains for frame alignment purposes. These time domains can be arranged in sets (faces) of 16 links. The selection of the time domains for each link interface is selectable through the software interface. * Supports STS-48 equivalent flows using SONET scrambling over LVDS links operating at 2.488. * Supports STS-12 equivalent flows using an extended 8B/10B protocol over LVDS links operating at 777.6 Mhz to support first generation CHESSTM interfaces. * Provides 65 ingress and egress STS-48 equivalent ports for a total of 65*48 = 3120 STS-1 flows. * Optionally supports 65 ingress and egress STS-12 equivalent ports for a total of 65*12 = 780 STS-1 flows. * Provides SONET scrambled 622 Mbit/s link operation, selectable per link face. * Supports non-blocking permutation switching at STS-1 granularity for the above supported flows. * Ports are grouped in sets (faces) of 16 links, and each face is configurable for STS-12 or STS-48 data rates. * Supports multi-plane (inverse multiplexed) switch architectures in conjunction with other CHESSTM components. * Interfaces to STS-192 devices by aggregating 16 STS-12, 8 STS-24, or 4 STS-48 equivalent flows. * Supports multicast and broadcast of STS-1 streams. * Detects and reports inactive or errored LVDS links via the microprocessor interface. * Supports two sets of switch settings (active and standby) and a controlled method of changing settings on STS-1 frame boundaries. * Supported by an efficient algorithm to compute control settings for all permutation loads for all supported fabric architectures. Algorithms are also available for multicast/broadcast allocation. OSYSCLK BLOCK DIAGRAM SYSCLK TJ0FPA CMP_A RP[1] RN[1] Receive LVDS (RXLV) #1 Data Recovery Unit (DRU) #1 Rx SONET Data Framer (RSEF) #1 Rx SONET Data Framer (RSEF) #2 Rx Time Slot Interchange (RTSI) #1 Rx Time Slot Interchange (RTSI) #2 CrossBar Space Switch Element (SSWE) RJOFP CMP_B TJ0FPB Tx Time Slot Interchange (TTSI) #1 Tx Data Scrambler/ Encoder (TSEC) #1 Tx Data Scrambler/ Encoder (TSEC) #2 Serializer (PISO) #1 Transmit LVDS (TXLV) #1 TP[1] TN[1] RP[2] RN[2] Receive LVDS (RXLV) #2 Data Recovery Unit (DRU) #2 Tx Time Slot Interchange (TTSI) #2 Serializer (PISO) #2 Transmit LVDS (TXLV) #2 TP[2] TN[2] * * * RP[64] RN[64] Receive LVDS (RXLV) #64 Data Recovery Unit (DRU) #64 Rx SONET Data Framer (RSEF) #64 Rx SONET Data Framer (RSEF) #65 Rx Time Slot Interchange (RTSI) #64 Rx Time Slot Interchange (RTSI) #65 * * * Tx Time Slot Interchange (TTSI) #64 Tx Data Scrambler/ Encoder (TSEC) #64 Tx Data Scrambler/ Encoder (TSEC) #65 Serializer (PISO) #64 Transmit LVDS (TXLV) #64 TP[64] TN[64] RP[65] RN[65] Receive LVDS (RXLV) #65 Data Recovery Unit (DRU) #65 Tx Time Slot Interchange (TTSI) #65 Serializer (PISO) #65 Transmit LVDS (TXLV) #65 TP[65] TN[65] Microprocessor Interface JTAG Clock Synthesis Unit Interface (CSUI) Clock Clock Clock Synthesis Clock Synthesis Synthesis UnitSynthesis (CSU) Unit (CSU) Unit (CSU) Unit (CSU) A [15:0] D [15:0] RSTB CSB WDB RDB ALE INTB REFCLK4N TRSTB TCK TMS TDI TDO REFCLK1N REFCLK4P REFCLK1P REFCLK2N REFCLK3N PRES1 PRES2 PRES3 REFCLK2P PMC-2001267 (P2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE REFCLK3P (c) Copyright PMC-Sierra, Inc. 2001. PRES4 Preliminary PM5374 TSE-160 160 Gbit/s Transport Switching Element * Driven by a 155.52 MHz reference clock. * Implemented in 1.8 V core and 3.3 V I/O, 0.18 m CMOS and packaged in a 1152 ball FCBGA. * Requires no external RAMs or logic parts. * Provides a standard IEEE 1149.1 JTAG port. * Supports a 16-bit microprocessor interface which is used to initialize the device, to write switch settings into onchip control tables, and to monitor device performance. APPLICATIONS * * * * Optical cross connects. Multi-service provisioning platforms. SONET/SDH Add/Drop Multiplexers. SONET/SDH Digital Cross connects. TYPICAL APPLICATIONS MULTI-SERVICE SWITCH Working and Protect 640 G PM5374 TSE-160 Fabric 2.488 Gbit/s Serial Backplane PM5307 TBS-9953 #1 2.488 Gbit/s Serial Backplane PM5307 TBS-9953 #33 SONET Side 1 PM5317 SPECTRA-9953 #1 Packet/Cell Side 1 PM7390 S/UNI-MACH-48 #1 Packets/Cells STS-48c or Smaller Channelization STS-192 PM5374 TSE-160 Working #1 PM5374 TSE-160 Protected #1 2 4 x STS-48 PM5317 SPECTRA-9953 #2 PM5307 TBS-9953 #2 2 PM5307 TBS-9953 #34 PM5390 S/UNI-9953 #2 Packets/Cells STS-192c or 4 x STS-48c PM5374 TSE-160 Working #2 PM5374 TSE-160 Protected #2 32 STS-192 PM5317 SPECTRA-9953 #32 * * * 2.488 Gbit/s Serial Backplane PM5307 TBS-9953 #32 2.488 Gbit/s Serial Backplane PM5374 TSE-160 Working #4 * * * 2.488 Gbit/s Serial Backplane * * * PM5390 S/UNI-9953 #32 32 Packets/Cells STS-192c or 4 x STS-48c PM5374 TSE-160 Protected #4 PM5307 TBS-9953 #64 2.488 Gbit/s Serial Backplane ADM Function Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PMC-2001267 (P2) (c) Copyright PMC-Sierra, Inc. 2001. All rights reserved. S/UNI is a registered trademark of PMC-Sierra, Inc. SPECTRA and CHESS are trademarks of PMCSierra, Inc. |
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